Solid-state imaging devices as represented by CMOS (Complementary Metal Oxide Semiconductor) image sensors have come to use WL-CSP (Wafer Level Chip Size Package). WL-CSP involves formation of terminals and wiring prior to cutting out chips from a semiconductor substrate.
WL-CSP fabrication steps include a process by which, for example, a fine vertical hole (VIA) is formed that opens to the metal pad inside a semiconductor substrate from the back of the semiconductor substrate. The formation of the vertical hole is a process that greatly influences the manufacturing cost of the semiconductor element.
The vertical hole has been formed in a silicon wafer using DRIE (Deep Reactive Ion Etching) as a preceding process. However, DRIE involves high device cost. Further, DRIE requires a photolithography step in which a photosensitive substance is exposed in patterns after being applied to a silicon wafer surface.
As a countermeasure, there has been proposed a process of forming a vertical hole in a silicon wafer using a substrate forming technique that makes use of a laser drill. The process using a laser drill forms a vertical hole in a substrate by irradiation of a laser beam, and does not require a photolithography step. Further, because a laser drill device is less expensive, the laser drill process is much more advantageous than the DRIE process in terms of manufacturing cost.
However, it is very difficult with a laser drill to, for example, control the process with such an accuracy that the drilling stops upon the vertical hole reaching the metal pad inside the semiconductor substrate.
In this connection, JP-A-2007-305995 discloses a semiconductor device fabrication process by which a metal bump is disposed on the metal pad inside a semiconductor substrate, and in which a vertical hole is formed with a laser drill that reaches the metal bump. In this process, the metal bump is used as a stopper for the laser drill forming the vertical hole. For example, a 15 μm-thick plated nickel is used as the metal bump.